THE IMPACT OF ANALOGUE TO DIGITAL AND DIGITAL TO ANALOGUE CONVERSION

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METHODOLOGY

SAR ADC Design Techniques

SAR architecture employs a binary search algorithm for analog-to-digital conversion. Conventional SAR ADC, which utilizes the charge redistribution through a switched-capacitor array, is shown in Fig. 1.1. A SAR ADC can be implemented with high resolution and relatively low power consumption (Huang, 2010, pp. 230). However, as it can resolve only one bit per cycle, the SAR ADC needs an N times faster clock to attain N-b resolution. For example, to drive a 10-b 100- MS/s SAR ADC with a synchronous clock, the clock generator has to provide a 1- GHz clock. This clocking overhead not only limits the ADC operation speed, but also increases digital power consumption of the clock generator.

Fig. 1.1 A conventional SAR ADC

Asynchronous Clocking

Fig. 1.2(a) shows a timing diagram of a conventional SAR ADC operated by a synchronous clock. In this timing scheme, the SAR control logic switches the capacitor array by the falling edge of clock QM and a regenerative latch in the comparator starts to latch by the rising edge of clock QM. However, this synchronous operation using both rising and falling edges of the clock causes inefficient use of cycle time. The timing scheme in Fig. 1.2(b) uses the same synchronous clock QM, but it is triggered only by the rising edge for synchronization, which brings more design freedom to assign the given cycle time more efficiently. In this ADC, SAR control logic is triggered right after the comparator makes a decision, and a preamplifier of the comparator has more time to amplify a signal (Choi, 2008, pp. 31).

This clocking idea can be extended further. Suppose the preamplifier has enough bandwidth to operate in a short amplification time, the previous output signal of the comparator can trigger not only control logic, but also the following clock itself, which will trigger the comparator in the following cycle. This recursive operation can be repeated until the ADC resolves its resolution, and the clock generator for clock QM is no longer needed, as shown in Fig. 1.3(a) (Huang, 2010, pp. 230).

This asynchronous clocking in a SAR ADC design has two advantages in comparison to synchronous clocking. As a clock trigger is generated right after a comparator resolves a previous output, each cycle period is automatically optimized as shown in Fig. 1.3(b), whereas every period is determined equally by the longest cycle period in a synchronous SAR ADC. Second, it can reduce power consumption from high-speed buffering in the clock ...