VHDL AND VGA DISPLAY

VHDL and VGA Display

VHDL and VGA Display

VHDL

VHDL is an acronym that represents the combination of VHSIC and HDL, where VHSIC stands for Very High Speed Integrated Circuit and is itself HDL stands for Hardware Description Language. It is a language defined by the IEEE (Institute of Electrical and Electronics Engineers) (ANSI / IEEE 1076-1993) used by engineers to describe digital circuits. Other methods for designing circuits are capturing schemes (with tools CAD) and block diagrams, but these are not practical in complex designs. Other languages for the same purpose are Verilog and ABEL.

Although it can be used generally to describe any circuit is mainly used for programming PLD (Programmable Logic Device - Programmable Logic Device), FPGA (Field Programmable Gate Array), ASIC and the like.

Ways to describe a circuit

Within the VHDL there are several ways you can design the same circuit and the task of choosing the most appropriate designer.

Functional describe how the circuit behaves. This is the most similar to the software language as the description is sequential. These statements are sequential in the so-called VHDL processes. The processes are executed in parallel with each other and in parallel with concurrent signal assignments and the bodies to other components.

Data Flow: Describes assignments concurrent (parallel) signals.

Structural: describes the circuit component instances. These instances form a higher-level design, connecting the ports of these instances the internal signals of the circuit, or ports higher-level circuit.

Mixed: combination of some or all of the above (Bryan, 2012).

In VHDL there are methodical ways to design state machines, digital filters, etc. test beds.

Design Sequence

The design of a flow system might be:

Division of the core designs in separate modules. Modularity is one of the main concepts of every design. Normally difference between two design methodologies: top-down and bottom-up. The top-down methodology is that a complex design is divided into more simple designs can be devised (or describe) more easily. The bottom-up approach is to build a complex design from modules already designed, simpler. In practice, one generally uses two design methodologies.

Input designs can be used various methods such as VHDL as seen above.

Functional simulation, i.e., we find that what is written in the previous section really works as we want, if you do not have to change it. In this type of simulation is found that the VHDL or Verilog code (or other language HDL) succeeds what is intended.

Synthesis. This step brings the old design (which we know works) to a particular hardware, either an FPGA or an ASIC. There language statements that are not synthesized, such exponentiation numbered divisions or non-constant. The fact that not all expressions are synthesizable VHDL is that the VHDL language is a generic system modeling (not only digital circuit design), so that there are expressions which cannot be transformed to digital circuits. During synthesis takes into account the internal structure of the device, and restrictions are defined as the pin assignments. The synthesizer optimized logical expressions in order to occupy less area, or is eliminated logical expressions that are not ...